1. Field of the Invention
The present invention relates to a semiconductor memory apparatus and, more particularly, to a word line arrangement of a memory cell array in a 1/4-pitch dynamic random access memory (to be referred to as a DRAM hereinafter).
2. Description of the Related Art
In a memory cell array in a conventional random access memory (to be referred to as a DRAM hereinafter), various arrangement patterns for obtaining high integration and a large capacity have been proposed. FIG. 1 schematically shows, as an example, a part of folded bit line type 1/2-pitch cell alignment pattern.
In FIG. 1, reference symbols BL.sub.1 to BL.sub.4 denote bit lines formed to be parallel to each other; MC denotes 1-transistor 1-capacitor memory cells; DC denotes dummy cells; WL1 to WL4 denote word lines; DWL14 and DWL23 denote dummy word lines; and SA.sub.1 and SA.sub.2 denote bit line sense amplifiers arranged on one side of a corresponding pair of the bit lines BL.sub.1 to BL.sub.4. The two adjacent bit lines (BL.sub.1 and BL.sub.2) and (BL.sub.3 and BL.sub.4) are complementarily paired to be connected to one of the bit line sense amplifiers SA.sub.1 and SA.sub.2.
With the cell alignment shown in FIG. 1, when the size of a memory cell is decreased in accordance with micropatterning of a semiconductor memory apparatus, a distance between openings of cell plate electrodes (capacitor plate electrodes) is decreased, thereby disconnecting the cell plate electrode. Therefore, in order to avoid the above problem, it is proposed that memory cells are arranged to be offset by a 1/2.sup.n (n is a natural number of 2 or more) pitch in a direction of a channel length of a cell transistor (charge transferring transistor) (for example, Published Unexamined Japanese Patent Application No. 61-274357).
FIG. 2 schematically shows a 1/4-pitch cell alignment pattern. In FIG. 2, reference symbols BL.sub.1 to BL.sub.4 denote bit lines formed to be parallel to each other; MC denotes 1-transistor 1-capacitor memory cells; DC denotes dummy cells; WL1 to WL4 denote word lines formed in a direction crossing the bit lines BL.sub.1 to BL.sub.4 ; DWL1 to DWL4 denote dummy word lines formed in a direction crossing the bit lines BL.sub.1 to BL.sub.4 ; and SA.sub.1 and SA.sub.2 denote bit line sense amplifiers arranged on both ends of the bit lines BL.sub.1 to BL.sub.4. The two bit lines (BL.sub.1 and BL.sub.3) and (BL.sub.2 and BL.sub.4) which sandwich one bit line are complementarily paired to be connected to one of the bit line sense amplifiers SA.sub.1 and SA.sub.2.
In the cell alignment pattern shown in FIG. 2, an element region for two transistors is formed to cross one bit line and two adjacent word lines. The drain (or source) of each of two cell transistors on the element region contacts the bit line at an intersection thereof. Regarding two arbitrary adjacent bit lines (e.g., BL.sub.1 and BL.sub.2), a memory contact portion of one bit line BL.sub.1 is arranged to be offset by a 1/4 pitch from the memory cell contact portion of the bit line BL.sub.2 adjacent to the memory contact portion of the bit line BL.sub.1 in a longitudinal direction of the bit line.
FIG. 3 is a plan view showing a part of the 1/4-pitch cell alignment pattern shown in FIG. 2 in detail. Referring to FIG. 3, reference numerals 611 denote bit lines formed in parallel to each other, and reference numerals 622 denote bit line sense amplifiers arranged on both ends of the bit lines 611. As shown in FIG. 3, bit lines 611 are complementarily paired and each pair is connected to a corresponding sense amplifier 622. Furthermore, the first or second bit line of any one pair of bit lines is arranged between the first and second bit lines of another pair of bit lines. The bit lines 611 have contact portions 633 with the drains (or sources) of the cell transistors arranged in the longitudinal direction of the bit lines 611 at a predetermined pitch P. In this case, the transistor contact portion 633 of a given bit line 611 is offset from the transistor contact portion of an adjacent bit line 611 by a 1/4 pitch in the longitudinal direction of the bit lines.
FIG. 4 shows a sectional structure of a memory cell region obtained when a 1/4-pitch cell alignment pattern is employed. In FIG. 4, denotes reference numeral 411 denotes a semiconductor substrate; 422, an element isolating field oxide film selectively formed on the substrate; 433 and 444 denote source regions of first and second cell transistors consisting of a diffusion layer of a conductivity type opposite to that of the substrate; 455 denotes a common drain region of the two cell transistors consisting of a diffusion layer of a conductivity type opposite to that of the substrate; and 466 and 477, gate electrodes of the first and second cell transistors which are formed on the substrate 411 through thin gate insulating films 488 and which are parts of word lines 722. Reference numeral 499 denotes a first insulating interlayer; 611, the bit lines; and 633, the transistor contact portions. The transistor contact portions contact the drain region 455 through contact holes. Reference numerals 722 denote the word lines; and 500, a second insulating interlayer.
Charge storing capacitors are respectively connected to the two cell transistors. That is, reference numerals 733 denote capacitor storing electrodes, and they are partially formed on the second insulating interlayer 500 on the upper side of parts of the bit lines 611 and contact the source regions 433 or 444 of the cell transistors through contact holes. A capacitor plate electrode 522 is formed opposite to each capacitor storing electrode 733 through a capacitor insulating film 511 having a thin part. Thus, a stacked capacitor is formed.
FIG. 5 shows a part of a conventional word line drive system in the above 1/4 pitch DRAM. In FIG. 5, reference numeral 61 denotes a boosted word line potential generating circuit for generating a word line signal WDRV boosted to a predetermined value of a power source potential or more, and reference numeral 62 denotes a predecoder for predecoding 2 bits X.sub.0 and X.sub.1 of a row address signal and selectively outputting four boosted word line signals WDRV1 to WDRV4. The predecoder comprises a predecoding gate circuit group 63 and a MOS transistor group 64 controlled in response to an output from the gate circuit group 63 to be an ON state so as to pass the boosted word line signal WDRV from the boosted word line signal generating circuit. Reference numeral 65 denotes a row decoder for decoding remaining bits X.sub.2 to X.sub.n of the row address signals; and 66, a word line drive circuit for outputting the boosted word line signals WDRV1 to WDRV4 to corresponding word lines WL1 to WL4 in response to an output from the row decoder 65. The word line drive circuit 66 comprises a MOS transistor group 67 controlled to be an ON state in response to the output from the row decoder 65 so as to pass the boosted word line signals WDRV1 to WDRV4 from the MOS transistor group 64 of the predecoder 62.
Note that, when the word lines WL1 to WL4 have large parasitic capacitances, the rise time of the word line potential is delayed. Therefore, the boosted word line signals WDRV1 to WDRV4 are used to prevent the above phenomenon.
As the size of a memory cell of the semiconductor memory apparatus is decreased, pitches between the word lines WL1 to WL4 are decreased. Each pattern pitch of the row decoder 65 and the word line drive circuit 66 for selecting the word lines WL1 to WL4 is hard to be increased. Under the above condition, when the row decoder 65 group and the word line drive circuit 66 group are to be aligned, in order to repeatedly arrange the pattern of the word line drive circuits 66 in the same repetition (non-inverted repetition) pattern in a direction of the alignment of the word lines, transistors of the word line drive circuits 66 must be electrically isolated from each other by element isolation. Therefore, the pattern of the word line drive circuit 66 is too large, thereby increasing the chip size.
As shown in FIG. 6, in order to prevent an increase in chip size, patterns of the word line drive circuits must be arranged such that every other word line drive circuit patterns are repeatedly inverted in the direction of the alignment of the word lines (a normal word line drive circuit is represented by 66a, and a pattern-inverted word line drive circuit is represented by 66b).
In the repeatedly inverted pattern, the source of a word line drive transistor selected by the word line drive circuit 66a or 66b and the source of a word line drive transistor selected by the adjacent word line drive circuit 66b or 66a are commonly used. That is, four MOS transistors N1 to N4 in each of the word line drive circuits 66a and 66b are arranged at upper right, upper left, lower right, and lower left positions in the pattern surface, respectively, and sources of these MOS transistors and sources of MOS transistors of the word line drive circuit adjacent to the word line drive circuits 66a and 66b are commonly formed to be connected to any one of the boosted word line signals WDRV1 to WDRV4.
With the above repeatedly inverted pattern, alignment of the word lines WL1 to WL4 determined by the boosted word line signals WDRV1 to WDRV4 is repeatedly inverted in units of word line drive circuits. For example, the word lines are repeatedly aligned in an order of WL1.fwdarw.WL2.fwdarw.WL3.fwdarw.WL4.fwdarw.WL5.fwdarw.WL4.fwdarw.WL3.fwda rw.WL2.fwdarw.WL1.
In this case, a connecting relationship between the word lines WL1 to WL4 connected to the two adjacent word line drive circuits 66a and 66b and memory cells connected to two pairs of every two bit lines in 1/4-pitch system is different from that in a 1/2 pitch system. That is, in the 1/4-pitch cell alignment pattern, word lines (WL1 and WL2) connected to the word line drive circuit 66a and word lines (WL4 and WL3) connected to the word line drive circuit 66b are connected to memory cells MC connected to a bit BL.sub.3 of one bit line pair, and word lines (WL3 and WL4) connected to the word line drive circuit 66a and word lines (WL2 and WL1) connected to the word line drive circuit 66b are connected to memory cells MC connected to a bit line BL.sub.1 of one bit line pair. Word lines (WL2 and WL3) connected to the word line drive circuit 66a and word lines (WL3 and WL2) connected to the word line drive circuit 66b are connected to memory cells MC connected to a bit line BL.sub.2 of the other bit line pair, and word lines (WL1 and WL4) connected to the word line drive circuit 66a and word lines (WL4 and WL1) connected to the word line drive circuit 66b are connected to memory cells MC connected to a bit line BL4 of the other bit line pair.
On the contrary, in the 1/2-pitch cell alignment pattern, as shown in FIG. 1, word lines (WL1 and WL4) connected to each word line drive circuit are connected to memory cells MC connected to one bit line BL.sub.1 or BL.sub.3 of each pair of bit lines, and word lines (WL2 and WL3) connected to each word line drive circuit are connected to memory cells MC connected to the other bit line BL.sub.2 or BL.sub.4 of each pair of bit lines. That is, the word lines WL1 to WL4 of each word line drive circuit are repeatedly formed in the same pattern and connected to the memory cells MC in the same pattern.
When the above arrangement of the word lines is employed, as a dummy word line drive circuit for selecting dummy cells DC connected to the other bit line paired with one bit line to which memory cells selected by a selection word line is connected, an arrangement shown in FIG. 7 is used in the 1/2-pitch DRAM, and an arrangement shown in FIG. 8 is used in the 1/4-pitch DRAM.
That is, in a dummy word line drive circuit of a 1/2-pitch DRAM has the following arrangement. As shown in FIG. 7, one bit X.sub.0 of a row address signal and a boosted word line signal WDRV are logically processed by a logic circuit 81, and a dummy word line drive signal DWL14 is output during selection of the word line WL1 or WL4. A dummy word line drive signal DWL23 is output during selection of the word line WL2 or WL3.
A dummy word line drive circuit in a 1/4-pitch DRAM, as shown in FIG. 8, comprises a predecoder (not shown) for predecoding 2 bits X.sub.0 and X.sub.1 of a row address signal and selectively outputting four word line signals WDRV1 to WDRV4 and a logic circuit 91 for selectively outputting four dummy word line drive signals DWLa to DWLd in response to a row address signal (1 bit Xi of signals X2 to Xn input to the row decoder 65) for checking whether the pattern of the word line drive circuit used to select word lines is inverted or not. This logic circuit 91 comprises eight gate circuits 921 to 928 each for ORing two predetermined signals of the four boosted word line signals WDRV1 to WDRV4, four MOS transistors 931 to 934 controlled in an ON state by the 1-bit row address signal Xi to cause outputs from the four gate circuits of the eight gate circuits 921 to 928 to pass, and four MOS transistors 935 to 938 controlled in an ON state by an inverted signal Xiof the 1-bit row address signal Xi to cause outputs from the remaining four of eight gate circuits 921 to 928 to pass. Output terminals of the four MOS transistors 935 to 938 are wired-ORed to the output terminals of the MOS transistors 931 to 934 respectively.
Although the dummy word line drive circuit shown in FIG. 7 in the above 1/2-pitch DRAM has a simple arrangement, the dummy word line drive circuit in the 1/4-pitch DRAM is required to have a large number of circuit elements. A pattern area for the dummy word line drive circuit in which the pattern is repeated proportionally to the number of memory cell arrays is largely increased, thereby increasing the chip size. In addition, when dummy word line selection logic is complicated, the operational speed of the memory is adversely affected.
As described above, in a conventional 1/4-pitch DRAM, when the word line drive circuits are arranged such that every other word line drive circuit pattern is repeatedly inverted, logical processing for checking whether the pattern of the word line drive circuit used to select word lines is inverted or not must be performed by a dummy word line drive circuit. Therefore, since the dummy word line drive circuit is required to have a large number of circuit elements, the chip size is increased, and the dummy word line selection logic is complicated. The operational speed of the memory is undesirably decreased.